DRAM with stacked memory cell and PDL is known. PDL is a circuit used to precharge and balance a pair of digit lines with a power source or ground level when a rewriting into memory cell is completed after amplifying a memory cell data. PDL has a form distinct from that of the memory cells.
In a place, such as a memory cell array, that a high-density pattern is regularly disposed, a pattern deformation can happen around the border where the pattern regularity is deteriorated. This is called `micro-loading effect`. Namely, it is a phenomenon that an etching speed is reduced as a diameter of hole or etching width is shortened.
When PDL is disposed in a memory cell array, stacked polysilicon may be deformed by micro-loading effect, and thereby the cell capacitance around PDL may be dispersed.
Also, when a dummy word line is disposed to suppress the dispersion of cell capacitance, the layout size has to be increased.